*////////////////////////////////////////////////////////////////////// * (C) National Semiconductor, Inc. * Models developed and under copyright by: * National Semiconductor, Inc. *///////////////////////////////////////////////////////////////////// * Legal Notice: This material is intended for free software support. * The file may be copied, and distributed; however, reselling the * material is illegal *//////////////////////////////////////////////////////////////////// * For ordering or technical information on these models, contact: * National Semiconductor's Customer Response Center * 7:00 A.M.--7:00 P.M. U.S. Central Time * (800) 272-9959 * For Applications support, contact the Internet address: * amps-apps@galaxy.nsc.com * \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ * LM13700 Dual Operational Transconductance Amplifier * \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ * * Amplifier Bias Input * | Diode Bias * | | Positive Input * | | | Negative Input * | | | | Output * | | | | | Negative power supply * | | | | | | Buffer Input * | | | | | | | Buffer Output * | | | | | | | | Positive power supply * | | | | | | | | | .SUBCKT LM13700/NS 1 2 3 4 5 6 7 8 11 * * Features: * gm adjustable over 6 decades. * Excellent gm linearity. * Linearizing diodes. * Wide supply range of +/-2V to +/-22V. * * Note: This model is single-pole in nature and over-estimates * AC bandwidth and phase margin (stability) by over 2X. * Although refinement may be possible in the future, please * use benchtesting to finalize AC circuit design. * * Note: Model is for single device only and simulated * supply current is 1/2 of total device current. * ****************************************************** * C1 6 4 4.8P C2 3 6 4.8P * Output capacitor C3 5 6 6.26P D1 2 4 DX D2 2 3 DX D3 11 21 DX D4 21 22 DX D5 1 26 DX D6 26 27 DX D7 5 29 DX D8 28 5 DX D10 31 25 DX * Clamp for -CMR D11 28 25 DX * Ios source F1 4 3 POLY(1) V6 1E-10 5.129E-2 -1.189E4 1.123E9 F2 11 5 V2 1.022 F3 25 6 V3 1.0 F4 5 6 V1 1.022 * Output impedance F5 5 0 POLY(2) V3 V7 0 0 0 0 1 G1 0 33 5 0 .55E-3 I1 11 6 300U Q1 24 32 31 QX1 Q2 23 3 31 QX2 Q3 11 7 30 QZ Q4 11 30 8 QY V1 22 24 0V V2 22 23 0V V3 27 6 0V V4 11 29 1.4 V5 28 6 1.2 V6 4 32 0V V7 33 0 0V .MODEL QX1 NPN (IS=5E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2) .MODEL QX2 NPN (IS=5.125E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2) .MODEL QY NPN (IS=6E-15 BF=50) .MODEL QZ NPN (IS=5E-16 BF=266) .MODEL DX D (IS=5E-16) .ENDS *$ * \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ * Experimental xx3080 derived from LM13700 Dual Operational Transconductance Amplifier * Warning: It's not from National Semiconductor * \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ * * Amplifier Bias Input * | Diode Bias * | | Positive Input * | | | Negative Input * | | | | Output * | | | | | Negative power supply * | | | | | | Buffer Input * | | | | | | | Buffer Output * | | | | | | | | Positive power supply * | | | | | | | | | *.SUBCKT LM3080/NS 1 3 4 5 6 11 .SUBCKT LM3080/NS in- in+ vee bias out vcc * * Features: * gm adjustable over 6 decades. * Excellent gm linearity. * Linearizing diodes. * Wide supply range of +/-2V to +/-22V. * * Note: This model is single-pole in nature and over-estimates * AC bandwidth and phase margin (stability) by over 2X. * Although refinement may be possible in the future, please * use benchtesting to finalize AC circuit design. * * Note: Model is for single device only and simulated * supply current is 1/2 of total device current. * ****************************************************** * C1 vee in- 4.8P C2 in+ vee 4.8P * Output capacitor C3 out vee 6.26P D1 2 in- DX D2 2 in+ DX D3 vcc 21 DX D4 21 22 DX D5 bias 26 DX D6 26 27 DX D7 out 29 DX D8 28 out DX D10 31 25 DX * Clamp for -CMR D11 28 25 DX * Ios source F1 in- in+ POLY(1) V6 1E-10 5.129E-2 -1.189E4 1.123E9 F2 vcc out V2 1.022 F3 25 vee V3 1.0 F4 out vee V1 1.022 * Output impedance F5 out 0 POLY(2) V3 V7 0 0 0 0 1 G1 0 33 out 0 .55E-3 I1 vcc vee 300U Q1 24 32 31 QX1 Q2 23 in+ 31 QX2 *Q3 vcc 7 30 QZ *Q4 vcc 30 8 QY V1 22 24 0V V2 22 23 0V V3 27 vee 0V V4 vcc 29 1.4 V5 28 vee 1.2 V6 in- 32 0V V7 33 0 0V .MODEL QX1 NPN (IS=5E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2) .MODEL QX2 NPN (IS=5.125E-16 BF=200 NE=1.15 ISE=.63E-16 IKF=1E-2) .MODEL QY NPN (IS=6E-15 BF=50) .MODEL QZ NPN (IS=5E-16 BF=266) .MODEL DX D (IS=5E-16) .ENDS *$ .subckt ca3080a In+ In- Vcc Vee Out bias V1 Vcc 1 0 F1 Vcc 5 V1 1 D1 1 2 1v4 Q1 2 In- 4 0 n1 Q2 3 In+ 4 0 n1 Q3 4 bias Vee 0 n1 D2 bias Vee pn D3 6 3 pn D4 5 7 pn Q4 Out 3 6 0 p1 Q5 Out 5 7 0 n1 D5 Vcc 6 1v4 D6 7 Vee 0v6 C1 Out Vee 3p .model 0v6 D(Ron=20 Vfwd=0.6) .model 1v4 D(Ron=20 Vfwd=1.4) .model pn d(Is=1f Rs=18 Cjo=1p) .model n1 npn(Is=1f Bf=65 Vaf=5k Rb=500 Rc=5 Re=15 Cjc=2p Cje=2p) .model p1 pnp(Is=1f Bf=65 Vaf=5k Rb=500 Rc=5 Re=15 Cjc=1p Cje=3p) .ends * * LM3080 derived from NTE996 datasheet by Robertugo_2005 .subckt lm3080 in- in+ vee bias out vcc Q1 2 3 vcc 0 P Q2 4 2 3 0 P D1 vcc 3 D Q3 2 in- 1 0 N Q4 5 in+ 1 0 N Q5 5 6 vcc 0 P Q6 1 bias vee 0 N D2 bias vee D Q7 out 5 6 0 P D3 vcc 6 D Q8 out 4 7 0 N Q9 4 7 vee 0 N D4 7 vee D .model D D(IS=1E-16) .model N NPN .model P PNP .ends * .subckt ca3080 in- in+ vee bias out vcc Q4 1 4 vcc 0 P Q6 6 5 4 0 P Q5 6 1 5 0 P D3 vcc 4 D D2 1 5 D Q7 3 9 vcc 0 P Q1 1 in- 2 0 N Q2 3 in+ 2 0 N Q3 2 bias vee 0 N D1 bias vee D Q8 out 3 8 0 P D4 3 8 D Q9 out 8 9 0 P D5 vcc 9 D Q10 out 7 10 0 N Q11 7 10 vee 0 N D6 10 vee D .model D D .model N NPN .model P PNP .ends *