**************************************************
* Inverting buffer
* tpd 100n
* tr 160n/60n
.SUBCKT CD4049B  A Y  VDD VGND  vdd1={vdd} speed1={speed} tripdt1={tripdt}
.param td1=1e-9*(100-40-10)*5/{vdd1}*{speed1}
*
XIN1  A Ai  VDD VGND  CD40_IN_1  vdd2={vdd1}  speed2={speed1}  tripdt2={tripdt1} 
*
A1  Ai 0 0 0 0  Yn 0 0  BUF  tripdt={tripdt1}  td={td1}  
*
XOUT  Yn Y  VDD VGND  CD40_OUT_2X  vdd2={vdd1} speed2={speed1}  tripdt2={tripdt1}
.ends 4049
**********************************************************
*
* 7-stage Binary Ripple Counter
* CP->Q1 tpd 180ns
* Qn->Qn+1 tpd=90n
* R->Q tpd=140ns
* tr 100n
.SUBCKT CD4024B  MR CP Q1 Q2 Q3 Q4 Q5 Q6 Q7  VDD VGND  vdd1={vdd} speed1={speed} tripdt1={tripdt}
.param td1=1e-9*(180-90-40-10)*5/{vdd1}*{speed1}
*.param td2=1e-9*(140-90-40-10)*5/{vdd1}*{speed1}
.param td2=0
.param td3=1e-9*(90)*5/{vdd1}*{speed1}
*
XIN1  MR  MRi  VDD VGND  CD40_IN_1  vdd2={vdd1}  speed2={speed1}  tripdt2={tripdt1} 
XIN2  CP  CPi  VDD VGND  CD40_IN_1  vdd2={vdd1}  speed2={speed1}  tripdt2={tripdt1} 
*
AR   MRi 0   0 0 0   MRn MRp 0  BUF  tripdt={tripdt1}  td={td2}
AR0  MRi 0   0 0 0   MR0n  0 0  BUF  tripdt={tripdt1}  td={td1}
AC   CPi 0   0 0 0   0   C1p 0  BUF  tripdt={tripdt1}  td={td1}
ACP  C1p MR0n 0 0 0  CPn   0 0  AND  tripdt={tripdt1}
*
AFF1   Q1n  0 CPn  0 MRp  Q1n  Q1p  0  DFLOP  tripdt={tripdt1}  td={td3}
AFF2   Q2n  0 Q1n  0 MRp  Q2n  Q2p  0  DFLOP  tripdt={tripdt1}  td={td3}
AFF3   Q3n  0 Q2n  0 MRp  Q3n  Q3p  0  DFLOP  tripdt={tripdt1}  td={td3}
AFF4   Q4n  0 Q3n  0 MRp  Q4n  Q4p  0  DFLOP  tripdt={tripdt1}  td={td3}
AFF5   Q5n  0 Q4n  0 MRp  Q5n  Q5p  0  DFLOP  tripdt={tripdt1}  td={td3}
AFF6   Q6n  0 Q5n  0 MRp  Q6n  Q6p  0  DFLOP  tripdt={tripdt1}  td={td3}
AFF7   Q7n  0 Q6n  0 MRp  Q7n  Q7p  0  DFLOP  tripdt={tripdt1}  td={td3}
*
XOUT1  Q1p  Q1   VDD VGND  CD40_OUT_1X  vdd2={vdd1} speed2={speed1}  tripdt2={tripdt1}
XOUT2  Q2p  Q2   VDD VGND  CD40_OUT_1X  vdd2={vdd1} speed2={speed1}  tripdt2={tripdt1}
XOUT3  Q3p  Q3   VDD VGND  CD40_OUT_1X  vdd2={vdd1} speed2={speed1}  tripdt2={tripdt1}
XOUT4  Q4p  Q4   VDD VGND  CD40_OUT_1X  vdd2={vdd1} speed2={speed1}  tripdt2={tripdt1}
XOUT5  Q5p  Q5   VDD VGND  CD40_OUT_1X  vdd2={vdd1} speed2={speed1}  tripdt2={tripdt1}
XOUT6  Q6p  Q6   VDD VGND  CD40_OUT_1X  vdd2={vdd1} speed2={speed1}  tripdt2={tripdt1}
XOUT7  Q7p  Q7   VDD VGND  CD40_OUT_1X  vdd2={vdd1} speed2={speed1}  tripdt2={tripdt1}
.ends
*****************************************************
*================================================================
*
*   INPUT FILTERS
*
.MODEL CD40DIO1 D(Is=1e-12 Rs=100)
*
.SUBCKT  CD40_IN_0  in out  VDD VGND  vdd3={vdd2} speed3={speed2}  tripdt3={tripdt2} 
.param vt1=0.5
.param gain=(1/{vdd3})
*
*D1 0   in  CD40DIO1 
*D2 in VDD  CD40DIO1
R2 in VGND 1e8
E1 out20 0 in VGND {gain}
AE1  out20 0 0 0 0  0 out 0  BUF  ref={vt1}  vhigh=1  tripdt={tripdt3}
.ends
*
*
.SUBCKT  CD40_IN_1  in out  VDD VGND  vdd3={vdd2} speed3={speed2}  tripdt3={tripdt2} 
* 3ns input delay
*.param Cval = 0.55e-12*4/({vdd3}-0.5)*{speed3}
* 10ns delay @5V
.param Cval = 1.8e-12*5/{vdd3}*{speed3}
.param vt1=0.5
.param gain=(1/{vdd3})
*
*D1 0   in  CD40DIO1 
*D2 in VDD  CD40DIO1
R1 in out10 10k
C1 out10 VGND {Cval}
R2 in VGND 1e8
*E1 out20 0 out10 VGND {gain}
B1 out20 0 V=LIMIT(0,V(out10,VGND)*{gain},1)
AE1  out20 0 0 0 0  0 out 0  BUF  ref={vt1}  vhigh=1  tripdt={tripdt3}
.ends
*
*
* Schmitt-input; 2.9V/2.1V @5V
.SUBCKT  CD40_IN_S_1  in out  VDD VGND  vdd3={vdd2}  speed3={speed2}  tripdt3={tripdt2} 
.param Cval = 1.8e-12*5/{vdd3}*{speed3}
.param vt1=2.5/5
.param vh1=0.4/5
.param gain=(1/{vdd3})
*
*D1 0   in  CD40DIO1 
*D2 in VDD  CD40DIO1
R1 in out10 10k
C1 out10 VGND {Cval}
R2 in VGND 1e8
*E1 out20 0 out10 VGND {gain}
B1 out20 0 V=LIMIT(0,V(out10,VGND)*{gain},1)
AE1  out20 0 0 0 0  0 out 0  SCHMITT  vt={vt1} vh={vh1} vhigh=1  tripdt={tripdt3}
.ends
*
*
*======================================================================
*
* OUTPUT DRIVERS, LEVEL TRANSLATORS
*
* 
* Tristate switch
.MODEL SW_HC1 SW(Vt=0.5 Ron=1 Roff=1e6)
.MODEL SW_HC2 SW(Vt=0.5 Ron=1 Roff=1e6)
*
.MODEL DIO2 D(Is=1e-12 Rs=10)
*
* Standard output driver
.SUBCKT  CD40_OUT_1X  in out  VDD VGND  vdd3={vdd2} speed3={speed2}  tripdt3={tripdt2}
.param trise1=80e-9*5.0/{vdd3}*{speed3}
.param Rout=500*5.0/{vdd3}*{speed3}
*
AE1  in 0 0 0 0  0 out10 0  BUF  tripdt={tripdt3}  trise={trise1}
*
E1 out20 VGND out10 0 {vdd3}
Rout out20 out {Rout}
*D1 0   out  DIO2 
*D2 out VDD  DIO2
.ends
*
*
*
* Strong output driver
.SUBCKT  CD40_OUT_2X  in out  VDD VGND  vdd3={vdd2} speed3={speed2}  tripdt3={tripdt2}
.param trise1=80e-9*5/{vdd3}*{speed3}
.param Rout=250*5.0/{vdd3}*{speed3}
*
AE1  in 0 0 0 0  0 out10 0  BUF  tripdt={tripdt3}  trise={trise1}
*
E1  out20 VGND out10 0 {vdd3}
Rout  out20 out {Rout}
*D1 0   out  DIO2 
*D2 out VDD  DIO2
.ends
*
*
*
* Tristate output driver
.SUBCKT  CD40_OUT_TS_2X  en in out  VDD VGND  vdd3={vdd2} speed3={speed2}  tripdt3={tripdt2}
.param trise1=80e-9*5.0/{vdd3}*{speed3}
.param Rout=250*5/{vdd3}*{speed3}
*
A1  in 0 0 0 0  0 out10 0  BUF  tripdt={tripdt3}  trise={trise1}
*
E1  out20 VGND out10 0 {vdd3}
Rout  out20 out30 {Rout}
SW1  out30 out en 0 SW_HC1
*D1 0   out  DIO2 
*D2 out VDD  DIO2
.ends
*
*
*
* Open drain output driver 
.SUBCKT  CD40_OUT_OD_1X  in out  VDD VGND  vdd3={vdd2} speed3={speed2}  tripdt3={tripdt2}
.param trise1=80e-9*5/{vdd3}*{speed3}
.param Rout=500*5/{vdd3}*{speed3}
*
A1  in 0 0 0 0   out10 0 0  BUF  tripdt={tripdt3}  trise={trise1}
*
Rout  out30 VGND {Rout}
SW1  out30 out out10 0 SW_HC2
 *Alternative real output stage from CD40U04 would replace Rout and SW1
 *E1  out20 VGND out10 0 {vdd3}
 *Rout  out20 out30 {Rout}
 *MN1 out out30 VGND VGND  MHCNEN W=140U L=2.4U AD=200P AS=300P PD=10U PS=130U
 *MN2 out out30 VGND VGND  MHCNEN W=140U L=2.4U AD=200P AS=300P PD=10U PS=130U
 *MN3 out out30 VGND VGND  MHCNEN W=140U L=2.4U AD=200P AS=300P PD=10U PS=130U
*D1 0   out  DIO2 
*D2 out VDD  DIO2
.ends
*
*