* Modified for LTspice
* 
* PSpice Model Editor - Version 9.2.1
*$
.SUBCKT IXDN430YI  VCC OUT GND IN  NC 
R_R11         N494687 0  10k  
R_R3         N647678 0  10K  
X_U7A         N383201 N383201 N494687 VSS 0 74ACT00 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
R_R5         VCC N242309  10K  
X_U6A         N530707 N383201 VSS 0 74ACT14 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
R_R20         CON1B 0  10k  
R_R12         ENABLE 0  100k  
R_R4         UV 0  10k  
R_R15         CON1 0  10K  
X_U8A         N251978 UV N494687 ENABLE VSS 0 74ACT11 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U11A         N929952 CON1A VSS 0 74ACT14 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
R_R6         N242309 0  510  
X_U14A         N139106 N404483 N02959 VSS 0 74ACT02 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U4A         N647678 UV VSS 0 74ACT04 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U13A         CON1B N139106 N134432 VSS 0 74ACT00 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
R_R22         N139106 0  10k  
D_D3         IN VCC D1N4376 
C_C4         N538279 IN  5p  
R_R2         N647531 0  2.502k  
R_R14         N538279 0  4000  
R_R36         OUT 0  100K  
X_U10A         N336660 N929952 VSS 0 74ACT04 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
R_R13         IN N538279  4160  
X_U3A         N647531 N647678 VSS 0 74ACT14 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
D_D4         0 IN D1N4376 
R_R41         0 N336660  10k  
R_R1         VCC N647531  10k  
M_Q5         N104168 N04428 VCC VCC MPFET           
R_R33         VCC N04213  5.6K  
M_Q4         N04213 N681317 0 0 MNMOS           
R_R18         N404483 0  10k  
R_R7         EN N530707  0.5K  
X_U15A         N134432 N02959 N665658 VSS 0 74ACT32 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
R_R24         N665658 0  20k  
R_R34         VCC N04428  5.6K  
Q_Q2         N681317 N700910 0 FMMT918 
R_R43         0 CON1A  10k  
C_C2         VSS 0  100uF  
C_C1         VCC 0  220uF  
R_R10         N383201 0  10k  
R_R28         N665691 0  20k  
R_R29         N665691 N700910  1  
R_R9         N251978 0  10k  
M_Q3         N04428 N681472 0 0 MNMOS           
X_U2A         CON1 N336660 VSS 0 74ACT14 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
R_R25         N665658 N559550  1  
R_R38         0 GND  0.00001  
X_U16A         N02959 N134432 N665691 VSS 0 74ACT32 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
D_D1         N538279 VSS D1N4376 
R_R42         0 N929952  10k  
R_R26         N559550 0  10k  
R_R23         N134432 0  10k  
R_R19         ENABLE CON1B  100  
X_U9A         N538279 CON1 VSS 0 74ACT14 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U5A         N242309 N251978 VSS 0 74ACT14 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
R_R37         0 GND  0.00001  
R_R30         N700910 0  10k  
R_R21         CON1A N139106  0.0001  
R_R8         N530707 0  10K  
M_Q6         N104168 N04213 0 0 MNFET           
R_R35         N104168 OUT  0.51 
C_C3         VSS 0  0.1u  
X_U12A         CON1B N404483 VSS 0 74ACT04 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
R_R27         N02959 0  10k  
X_U1         VCC VSS 0 LM7805C
R_R32         VCC N681472  470  
D_D2         0 N538279 D1N4376 
R_R31         VCC N681317  470  
R_R40         EN VCC  10k  
Q_Q1         N681472 N559550 0 FMMT918 
****
.MODEL D1N4376 D  
.MODEL FMMT918 NPN IS =1.73E-13 BF =200 VAF=90 IKF=8.8E-3 ISE=241E-12 NE =1.701
+BR =3.124 VAR=9.7 NR =.9705 IKR=.02 ISC=8.31E-13 NC =1.112 RB =17 RE =2.13
+RC =30 CJE=2.27E-12 TF =.2E-9 CJC=1.2E-12 TR =1E-9 VJC=.415 MJC=.145
.MODEL MNMOS NMOS
+LEVEL=3 
+W=4E-6
+L=2E-6 
+ NSS = 0.00000E+00 VTO = 6.30000E-01 TOX = 1.90000E-08
+ XJ = 1.66632E-07 LD = 0.04000E-06 RSH = 6.40359E+02
+ NSUB = 1.82429E+16 NFS = 1.26963E+11 UO = 5.95254E+02
+ VMAX = 1.86907E+05 DELTA = 8.22502E-01 THETA = 5.77858E-02
+ ETA = 2.19310E-02 KAPPA = 2.60564E-01
+ CGSO = 7.263E-11 CGDO = 7.263E-11 CGBO = 1.11890E-10
+ CJ = 2.59E-04 CJSW = 2E-10 PB = 0.811
+ MJ = 0.36 MJSW = 0.31 TPG = 1
*+ DW =-0.18000E-06 DL =-0.72500E-06
+ XQC = 1
.MODEL MNFET NMOS(LEVEL=3 W=100e-3 L=0.0002e-006)
.MODEL MPFET PMOS(LEVEL=3 W=100e-3 L=0.0002e-006)
.ENDS
*$

.subckt 74ACT00 in1 in2 out VSS VCOM
A1 in1 in2 0 0 0 out 0 0 AND Td=5n Ref=1.5 Vhigh=5 Trise=3n
.ENDS

.subckt 74ACT02 in1 in2 out VSS VCOM
A1 in1 in2 0 0 0 out 0 0 OR Td=5n Ref=1.5 Vhigh=5 Trise=3n
.ENDS

.subckt 74ACT04 in1 out VSS VCOM
A1 in1 0 0 0 0 out 0 0 BUF Td=5n Ref=1.5 Vhigh=5 Trise=3n
.ENDS

.subckt 74ACT11 in1 in2 in3 out VSS VCOM
A1 in1 in2 in3 0 0 0 out 0 AND Td=5n Ref=1.5 Vhigh=5 Trise=3n
.ENDS

.subckt 74ACT14 in1 out VSS VCOM
A1 in1 0 0 0 0 out 0 0 SCHMITT Td=5n Vt=1.5 Vh=0.5 Vhigh=5 Trise=3n
.ENDS

.subckt 74ACT32 in1 in2 out VSS VCOM
A1 in1 in2 0 0 0 0 out 0 OR Td=5n Ref=1.5 Vhigh=5 Trise=3n
.ENDS
 
.subckt LM7805C VIN VOUT VCOM
B1 V1 0 V=limit(0,V(VIN)-1,5)
R1 V1 VOUT 0.1
C1 VOUT 0 100p
.ENDS

 
